Effects of local oscillator (LO) noise on RF systems:
In many RF systems, the Phase Noise of a LO clock source is a key concern in designing the system. An example of quadrature RF receiver is shown in FIG. 1, while an example of a quadrature RF transmitter is shown in FIG. 2.
In the quadrature RF Receiver of FIG. 1, an RF signal is received by an antenna 101, amplified by a Low-Noise Amplifier (LNA) 102, and then down-converted from RF to an Intermediate Frequency (IF) or Baseband (BB, sometimes also known as “Zero-IF” or ZIF) by mixing an output from the LNA 102 with two versions of a LO clock source using mixers 104. One copy of the LO clock source is shifted by a quarter phase, illustrated by a phase shifter 105. The outputs from the mixers 104 are then filtered by two Low-Pass Filters 106 for further processing. The Quadrature RF Transmitter of FIG. 2 is qualitatively similar, but operates in reverse. As shown in FIG. 2, two BB/IF signals are up-converted to RF using two mixers 204, summed together by a summing device 203, and finally amplified by a Power Amplifier (PA) 202 for transmission over an antenna 201. In these Figures, and in all succeeding figures in this document, an attempt is made to use common numbering schemes for common elements for clarity.
There are many alternate forms that RF systems can take beyond what is shown in FIG. 1 and FIG. 2, and the details of their construction are beyond the scope of this document; however, almost all structures involve mixing signals with LO clock sources to convert BB/IF signals to RF or vice versa. There are many possible mixer structures, and the details of their construction are also beyond the scope of this document, however at their core they can all be modeled as analog multipliers. Applying two sinusoidal inputs to an analog multiplier:i1=cos(2·π·f1·t)i2=cos(2·π·f2·t)  Equation 1
Results in:
                                          i            1                    ·                      i            2                          =                                            cos              ⁡                              (                                  2                  ·                  π                  ·                                      f                    1                                    ·                  t                                )                                      ·                          cos              ⁡                              (                                  2                  ·                  π                  ·                                      f                    2                                    ·                  t                                )                                              ⁢                                          ⁢          Equation          ⁢                                                            ⁢                                                          ⁢          2                                        =                              1            2                    ·                      (                                          cos                ⁡                                  (                                      2                    ·                    π                    ·                                          (                                                                        f                          1                                                +                                                  f                          2                                                                    )                                        ·                    t                                    )                                            +                              cos                ⁡                                  (                                      2                    ·                    π                    ·                                          (                                                                        f                          1                                                -                                                  f                          2                                                                    )                                        ·                    t                                    )                                                      )                              
In other words, the act of multiplying two pure sinusoids results in two other sinusoids, one at the “sum” frequency (i.e., f1+f2), the other at the “difference” frequency (i.e., f1−f2). In many RF applications, typically one of these two frequencies is desired while the other (known as the “image”) is not and is rejected at the output, using for example, filters or trigonometric identities.
FIGS. 3A and 3B show the Power Spectral Density (PSD) of one possible frequency plan for a Single-Frequency Receive RF system and shows the effect of LO Phase Noise at the output. Before the mixer, at FIG. 3A, an LO clock source 301 and an RF signal 311 are present, while after the mixer, FIG. 3B, there are two signals (two signal components), the desired “difference” signal 313 (frequency difference component) at IF and the undesired “sum” signal 314 (frequency sum component) at a much higher frequency, which can be removed with a Low-Pass Filter (e.g., the Low-Pass Filters 106 in FIG. 1). The effects of Phase Noise 302 on the LO clock source 301 (FIG. 3A) are also shown at FIG. 3B, and result in spectral growth of the RF signals 315 and 316 at the mixer output.
The LO Clock Source Phase Noise 302, when looked at on a PSD plot as in FIG. 3A, is usually expressed in the units of decibel per hertz with respect to carrier power, or dBc/Hz, i.e., the amount of Phase Noise power present in 1 Hz of bandwidth relative to the power of the LO tone.
In broadband applications such as telecommunication, Phase Noise is often expressed using terms such as Integrated RMS Jitter or Total Jitter, often measured in femtoseconds (fs) or picoseconds (ps). However in RF applications it is often more appropriate to talk about Phase Noise in dBc/Hz at certain frequency offsets from the carrier, for example “−153 dBc/Hz at 800 kHz offset”. To understand why, FIGS. 4A and 4B show a frequency plan for a multi-carrier RF Receiver, where the desired signal 411 is present but at a much lower power than a second signal (also known as a “Blocker” signal) at an adjacent carrier frequency 421. After being subjected to a mixer, the two output signals from the desired RF channel 411 (FIG. 4A) are present as signals 413 and 414 (FIG. 4B), as are the two output signals from the Blocker signal 421 (FIG. 4A), namely signal 423 and 424 (FIG. 4B).
As before, the Phase Noise 302 (FIG. 4A) on the LO Clock Source results in spectral regrowth, however in the multi-carrier scenario the spectral regrowth 425 from the high-power blocker 425 appears in the IF band of the down-converted signal 413. Because it is impossible to remove this noise from the IF signal, this irreparably harms the Signal-to-Noise Ratio (SNR) of the down-converted signal 413, limiting the available information-carrying bandwidth of the RF Receiver in that channel. The spectral regrowth 315 (FIG. 3B) of a single-carrier system is typically much less disruptive than in a multi-carrier system because the regrowth power is proportional to the signal power, whereas in a multi-carrier system, the regrowth power is proportional to the blocker's signal power, which, depending upon a number of factors, can be much higher.
Because Multi-Carrier RF Transmit systems are usually dealing with multiple RF signals of similar power, spectral regrowth concerns due to LO Phase Noise is often less of an issue than in Multi-Carrier RF Receive systems, but should still be considered.
Phase-Locked Loops and Phase Noise:
There is great deal of information known to those skilled in the art dealing with modeling of Phase Noise in general and LO Phase Noise in specific; however it is beyond the scope of this document to discuss this in great detail. In summary, all electronic components are capable of generating and modifying Phase Noise, with different generation or modification characteristics depending upon the component. It is, however, appropriate to provide some background on Phase Locked Loops and Phase Noise.
An elementary Phase Locked Loop (PLL) is shown in FIG. 5, and comprises a Phase Detector 501, a Loop Filter 502, and a Voltage-Controlled Oscillator (VCO) 503. The Phase Detector compares the relative phases of the Reference Clock input and the Output Clock from the VCO and, through negative feedback, produces a control signal that is in turn filtered by the Loop Filter to drive the VCO so that the relative phases of the two clocks are fixed.
The PLL of FIG. 5 has a simple configuration, however it demonstrates two key features. The first feature is that by locking the relative phases of the two inputs of the Phase Detector 501, the frequency of those inputs is also locked, i.e., the Output Clock frequency is the same as that of the Reference Clock.
The second key feature is that the PLL is a Phase Noise filter: every PLL has a loop bandwidth set by the characteristics of the loop components and, depending upon where Phase Noise is added in the system, this noise will see either a low-pass or a high-pass filter characteristic. For example, Phase Noise at the input to the Phase Detector 201 (coming either from the Reference Clock or from the Output Clock) will see a low-pass characteristic, whereas noise that arises from the VCO 503 will see a high-pass characteristic. Put another way, the Phase Noise seen at the Output Clock will be divided into two parts: below the loop bandwidth, the Output Clock Phase Noise will track the Phase Noise from the Reference Clock input (the Phase Noise from the PLL VCO component will be attenuated), while above the loop bandwidth, the Output Clock Phase Noise will track the Phase Noise generated by the VCO 503 (Phase Noise from the Reference Clock input will be attenuated).
It is important to note that the Phase Detector 501 is often a hybrid block, known as a Phase/Frequency Detector. During initial acquisition and while the frequencies at its input are radically different the block operates as a Frequency Detector, but when the input frequencies are close together the block operates as a Phase Detector. This dual operating mode is used to ensure reliable operation, and when alternative circuits are used for Phase Detection, provisions must be taken in the design to ensure that the block still locks to the correct frequency. The details of this are beyond the scope of this document but are well known to those skilled in the art.
Depending upon the required Phase Noise for the application and upon the components available, a system designer will attempt to choose a PLL bandwidth to meet these requirements. The designer is free to set the bandwidth as low as they desire, with practical limitations primarily arising from component choices for the Loop Filter 502, but the maximum bandwidth is limited by discrete-time effects to some fraction (often taken to be 1/10) of the Phase Detector input frequency. Assuming that the desire is for a low Phase Noise over a wide frequency range for use in a multi-carrier RF system and that an extremely low Phase Noise Reference Clock were available but the VCO had relatively large Phase Noise, the system designer would choose the PLL bandwidth to be as high as possible (for example, greater than or equal to the required low-noise frequency range) to suppress as much noise from the VCO as possible. Alternatively, if the Reference Clock had comparatively high Phase Noise (as is often the case if it is being provided by some sort of network timing system) but an extremely low Phase Noise VCO were available, the designer would choose a low PLL bandwidth (for example, lower (or much lower) than the carrier spacing) in order to suppress as much noise from the Reference Clock as possible.
The PLL of FIG. 5 is relatively limited because it passes its input frequency to its output with no modification. A more complex PLL, shown in FIG. 6, is capable of transforming one clock frequency to another by the addition of three dividers: a Feedback Divider 604, a Postscaler Divider 606, and a Prescaler Divider 607.
As before, once the PLL is locked, the inputs of the Phase Detector 501 are phase and frequency locked, however now the Output Clock frequency is determined by Equation 3:
                              F          OUT                =                                            F              REF                        M                    ·                      N            P                                              Equation        ⁢                                  ⁢        3            
The Feedback Divider 604 causes the VCO output to be a multiplied version of the Phase Detector input, while the Postscaler divider 606 and the Prescaler divider 607 both act to produce a Final Output Clock with a frequency that is a rational fraction of the Reference Clock frequency. Even though the Output Clock frequency is a rational fraction of the Reference Clock frequency, this PLL is commonly referred to as an Integer-N PLL because all dividers are integers. Phase Noise of the PLL of FIG. 6 is similar to that of FIG. 5, in that the Output Phase Noise has both low-pass and high-pass components, but there are several new considerations that must be taken into account. First the addition of three dividers has created three new sources of Phase Noise that must be considered in the system budget. Second, the Phase Noise due to the Reference Clock at the Output is now multiplied by the same factor N/(M·P) as the frequency multiplication of Equation 3, which means that low Phase Noise systems should ideally have comparatively low multiplication factors. Third, Phase Noise due to the Loop Filter 502 and the VCO 503 is attenuated by the Postscaler Divider 606, which creates new opportunities for low Phase Noise systems if the desired frequencies are comparatively low. Fourth, certain non-idealities in the Phase Detector 501 and Loop filter 502 can create a Phase Noise “spur” at an offset frequency equal to the Phase Detector frequency, which creates new constraints in system frequency planning. Finally, the inclusion of the Prescaler 607 divider results in a lower frequency Fref/M at the Phase Detector 501 input, which reduces both the maximum available loop bandwidth and brings the Phase Detector spur location closer in frequency to the desired output clock.
In flexible RF systems, the frequency spacing at the output from the frequency-generating PLL is important. For an Integer-N PLL, frequency spacing at the VCO output is set by the Phase Detector input frequency, FREF/M. Fine frequency spacing implies a comparatively low Phase Detector input frequency, however that requirement is at odds with what would be desirable for low Phase Noise: maximizing FREF while minimizing the multiplication factor N/(M·P). As a result, most RF systems use Fractional-N PLL's, instead of Integer-N PLL's.
An example of a Fractional-N PLL is shown at FIG. 7. The Fractional-N PLL replaces the Integer-N PLL fixed Feedback Divider 604 (FIG. 6) with a programmable Feedback Divider 704 and a Fractional-N Modulator 705 (FIG. 7). By introducing the programmable Feedback Divider 704 and the Fractional-N Modulator 705, the effective feedback divide ratio is given by Equation 4:
                              F          OUT                =                                                            F                REF                            M                        ·                                          X                _                            P                                =                                                    F                REF                            M                        ·                                          n                /                d                            P                                                          Equation        ⁢                                  ⁢        4            where X is the average value of X over time and X=n/d, where n and d are the Numerator and Denominator of a rational fraction and are inputs to the Fractional-N modulator 705, which is often implemented using Delta-Sigma (ΔΣ) techniques. The term Fractional-N comes from the inclusion of this rational fraction.
With this modification, the Phase Detector input frequency FREF/M can be significantly raised to no longer be the required frequency spacing, while at the same time, fine frequency resolution can be achieved by using large integer values for both n and d. In many practical Fractional-N PLL based Clock Generators, these coefficients are fairly large (perhaps 40 bits or more) to give ultra-fine frequency resolution. This increase of the Phase Detector frequency allows for wider PLL bandwidths and allows for the use of higher-frequency references, thereby reducing overall Phase Noise.
The addition of the Fractional-N divider subsystem (704 and 705) increases the Phase Noise seen at the input of the Phase Detector, however this Phase Noise will be attenuated by the PLL's low-pass filter characteristic before being seen at the output, and there are several techniques well known to those skilled in the art that allow for further reduction of low-frequency Phase Noise from this divider, minimizing its impact on the output.
Integrated Low Phase Noise LO Clock Generation Challenges:
The challenges of creating low Phase Noise LO clock sources in integrated forms are several. First and foremost, in many modern multi-carrier RF systems, low Phase Noise is required over frequency bands that cover extremely wide bandwidths, perhaps as high as 100-200 MHz. At the same time, the LO clock generator is required to have very fine frequency resolution, perhaps as low as 100 kHz. Additionally, the reference clocks available for generating the LO clock source are often derived from network timing references, and while they are extremely accurate in frequency, have poor Phase Noise characteristics.
Oscillators are fundamentally integrators, integrating frequency over time to produce phase, and are constructed by coupling an active circuit (an amplifier) to a narrow band-pass filter, often called a “resonator”. The better the Quality factor (also known as “Q” defined as the resonance frequency divided by the resonance width) of the band-pass filter and the lower the noise of the amplifier, the lower the oscillator Phase Noise will be. In an integrated circuit (IC) there are many oscillator topologies possible, however in general the highest-Q topologies use an Inductor-Capacitor (LC) tank network as the band-pass filter, and in general most integrated LC oscillators are limited to Q factors of 20 or so.
In comparison, Quartz Crystal oscillators can have Q factors greater than 10000, however they are impossible to fabricate using standard IC technologies. Crystal oscillators can be packaged with standard ICs, but they require specialized packaging techniques including hermetic sealing. In addition, Quartz Crystal oscillator frequencies are comparatively low (10-100 MHz), and require comparatively large multiplication factors to use for many modern RF systems. Surface Acoustic Wave (SAW) devices (Q factors of 1000 or more) have been used as resonators in oscillators, however they are physically large and also require specialized packaging and as a result are comparatively expensive. Micro Electrical-Mechanical Systems (MEMS) based resonators (Q factors of 1000 or more) are readily fabricated with standard IC processing and are relatively inexpensive; however they have comparatively low oscillation frequencies (10-100 MHz). Bulk Acoustic Wave (BAW) devices are qualitatively similar to MEMS, have Q factors of 500 or more, are relatively easily packaged together with standard IC devices, are relatively inexpensive, and operate at high frequencies, 0.5-3 GHz. Because of their relatively high Q factors and low Phase Noise, relative inexpensiveness, and potential for integration with standard IC fabrication and packaging technology, both MEMS and BAW devices are potentially attractive for applications in integrated RF LO clock generation. However, because of their manufacturing tolerances, both have significant part-to-part center frequency variation and additionally have significant temperature variation which must be taken into account. Finally, neither is tunable over the range of frequencies required for a modern multi-carrier RF system.
Integer-N PLL technology is capable of producing low Phase Noise at its output, provided it has either a low-Phase Noise Reference and a high PLL bandwidth or a low Phase Noise VCO and a low PLL bandwidth. To have a flexible output (controllable frequency output over a pre-determined frequency range), it requires either an extremely low frequency input and a high multiplication factor or a flexible frequency input. Taken together, these characteristics make it a poor fit on its own to creating an integrated Low Phase Noise LO clock source for a modern multi-carrier RF system.
Fractional-N PLL technology can provide extremely good frequency flexibility and can operate from relatively high frequency reference clocks, but normally requires relatively low PLL bandwidths in order to attenuate the Fractional-N Modulator noise from the output, which in turn requires either a high Postscaler divider ratio or a low Phase Noise VCO in order to produce low Phase Noise output. The low PLL bandwidth is compatible with the reference clock characteristics, however the high Postscaler divider ratio is often incompatible with the required LO frequency. As a result, a Fractional-N PLL taken on its own is also a poor fit to creating an integrated Low Noise LO clock source.
Therefore, improvements in low noise LO clock signal sources are desirable.